Intel nehalem by mel byt vydan ke konci roku 2008 s integrovanym pametovym radicem a podporou nejen DDR3, ale i dalsich novinek....
osmijadro:
Beckton
nejspis scoket LGA1366 nebo LGA1566 a 24MB L2 cache
TDP 130+
ctyrjadra budou rady:
Bloomfield
socket LGA1366 a 8MB L2 cache
Tylersburg severni mustek pres sbernici QPI, jizni pres ICH-10
TDP kolem 80-130W
vydan konec roku 2008
Lynfield, Clairkfield
socket LGA1160 s L2=8MB
komunikace jen pres jizni mustek “Ibexpeak” PCH
TDP 95W
vydani 2009
Havendale-dvoujadro
socket LGA1160 s L2=4MB
komunikace znovu pres “Ibexpeak” PCH, integrovana grafika
TDP kolem 95W
vydani v prubehu 2009
zakladni schema:
A newska z poslednich dni:
The Nehalem is Beta testing phase, Intel have not yet been made to provide a framework for micro-Nehalem White Paper, and even the motherboard industry Nehalem micro-architecture cognitive only on the United States last year old IDF General Assembly only on the information in the integrated motherboard industry received Intel's message, we have summarized the following points:
1. Nehalem majority of the micro-architecture design is derived from Yorkfield and Wolfdale, and has four original core design.
2. Nehalem will support similar to the SMT Hyper-Threading technology, and multi-threaded computing performance behalf Penryn micro-architecture is higher than 1.2 x - 2x.
3. Nehalem will be single-threaded computing performance behalf Penryn than 1.1 micro-structure of the x-1.25x.
4. Nehalem substantially strengthen the low load and the idle power consumption, further reducing leakage situation.
5. Nehalem in the same power and performance under the 30 percent increase in Penryn behalf, or in the same performance under the 30 percent decline in power.
6.7 Group SSE4.2 new orders, mainly to strengthen Database operations, and accelerates data transmission efficiency, DB server performance increases significantly.
It is worth noting that Intel Nehalem desktop products will be added to Turbo Mode design, which is similar to the Centrino platform IDA (Enhanced Dynamic Acceleration) technology, as part of a pastime to the core, while others will enter the core Turbo Bin state, Core clock will be increased to further enhance performance.
It is understood that the Turbo Mode will be the processor power consumption, temperature and size limit, the situation in the security and stability under acceleration, and multi-threaded part of the author to accelerate the completion of single-threaded. Principle is the mechanism through ACPI Terminology observed processors P1 and P0 idle state to enter the core of LMF (Lower Frequency Mode) state is the core of the operation to upgrade its clock, and enhancing the TDP will be no more than normal Under all the core operation of the maximum TDP specifications, which will make more energy-efficient processors.